Various companies currently have electronic systems with multiple high-speed—I/O interfaces in development. These systems and interfaces must meet various industry standard signal integrity specifications, such as, for instance for the HDMI standard there is an HDMI compliance specification. Additionally, there are also industry wide ESD/EOS (electrical overstress) survivability ratings. The target signal integrity requirement for many of these systems ensures system interoperability via BERT testing, eye-diagram masks, or passive TDR transmission line analysis.
A simplified example of a conventional system that implements ESD/EOS protection is illustrated in FIG. 1. It is noted that the system shown below could utilize typical shunt-type ESD clamps, or series-type ESD protection where the signals come in one side, and come out geometrically identical on the other side. The objective of these high-speed applications is to include the ESD protection without inserting an appreciable impedance discontinuity along the transmission line from the connector (P1) to the receiver or transmitter ASIC (DUP).
Conventional systems have a Device under Protection (DUP) and a Device under Test (DUT), in which there is a “shunt-architecture” in which the ESD Products have DUT in parallel with DUP. In a conventional ESD structure with a diode, one terminal is corrected to the signal line and the other terminal is connected to Ground. Therefore, in such a configuration, the ESD diode is always in parallel with the DUP. In these existing devices, such as a CM1213 from CMD, series parasitic resistance and inductance of the DUT work against drawing ESD current away from the DUP, and the parallel parasitic capacitance creates an impedance discontinuity in the frequency band of interest.
In conventional DUT's the chip bondwire and other parasitic inductance presents a high impedance at high frequencies and fast pulse edge rates (ie. during an ESD event). The amount of current drawn away from the DUP is hindered by the bondwire and these parasitic elements. As a result, the DUP is still largely directly exposed to the ESD threat, as illustrated below.
In-band, the parasitic capacitive load of the ESD clamp circuit, shown here as C(PAR), can drop the impedance of the transmission line form the connector to the ASIC (DUP) in the vicinity of the ESD DUT. To offset this, standard practice is to adjust (typically increase) the characteristic impedance of the transmission lines around the vicinity of the DUT to offset this (typically lower) impedance discontinuity of the ESD DUT placement.